Common Electrical I/O

MEETING NEW CHALLENGES – GENERATION AFTER GENERATION

The cloud has been transforming the way the world works for over a decade now, and new advancements in Artificial Intelligence (AI) and Machine Learning (ML) will change how every person in the world lives over the next ten years. At the heart of the cloud are the largest and most important networks operated by a handful of companies, but most users don’t realize who they are and the effort that goes on behind the scenes to allow that network to be created, operated and iteratively upgraded.

OIF’s Common Electrical I/O (CEI) is the building block that allows the cloud to evolve at break-neck speeds. Ethernet Switch-based 25G SERDES lane shipments have exceeded 100M since inception and are now a more common technology than 10G SERDES lanes in the data center. 50G SERDES are just starting to ship and will usher in a new wave of products. Without these high-speed building blocks, bandwidth in the data center could not grow at its current pace and Ethernet would not be the most dominant and robust networking technology across the world.

IDENTIFYING FUTURE NEEDS AND SOLUTIONS

OIF brings together people from many different disciplines: professionals with expertise as operators, players in the component market, and designers from system companies, resulting in a better project outcome. Getting things done quickly often helps move the industry forward in a more positive way.

One of the earliest OIF projects was the CEI, which started in about 2002.  Those original efforts led to 10G SERDES and common port interfaces across technologies, such as Fibre Channel (FC) and Ethernet sharing similar features at 8 Gbps and 10 Gbps respectively. OIF adopted a central and important role to next generation technologies by taking on this work and in many ways is the organization behind the cloud hyperscalers’ demand for higher bandwidth. Without OIF, the pace of innovation in the industry would not be as brisk as it has been, and the industry would not be pushing towards 400 and 800 Gbps port speeds by 2020.

It takes about three years to deliver a new generation of SERDES speeds to Ethernet switches, and the electrical interface standards often become a starting point or unofficial input for other standards bodies. OIF’s process is not as simple as many people think and starts a lot earlier than the specs we see out of the IEEE. In many ways, the work OIF does creates a community that the rest of the industry leverages and uses to ensure a commonality-based framework for many groups (Ethernet, Fibre Channel, SAS, InfiniBand, proprietary computing centers). If we look historically, FC and InfiniBand have used the similar electrical interfaces allowing for lower cost and better standardization of the supply chain. This commonality has helped improve supply chain costs, and in some cases, we have seen the same port form factor across all four technologies as a result.

As an example of OIF moving the industry, OIF members helped guide some of the designs to allow the introduction of chiplets, a design approach just now taking off. Chiplets will be critical to next generation systems designs. Ethernet Switch chips have an analog and a logic component to them. In the past, both of these would need to shrink at similar paces to reside on the same silicon. The analog part of chip design often will not shrink, even when implemented in the latest process technology.  But, with chiplets, the analog part of the design doesn’t have to shrink at the same pace as the logic component and in fact is more cost effective if it isn’t forced to move to a new process. This de-coupling of technology will allow for older and proven analog chip components to be packaged along with finer line process geometry-based logic chips. And, this disaggregated approach will result in lower cost systems with better yield, a positive outcome for the entire industry. Additional chiplet benefits include better thermal performance (e.g. better power), faster time to market and interchangeable components.  Chiplets can also allow different IP to be packaged together as the SERDES and logic can come from different companies. OIF recognized this trend and is addressing it with the current CEI-112G development efforts where die-to-die and chip-to-chip channels are being defined.

HELPING GET TECHNOLOGY TO MARKET FASTER

OIF has been busy at work and has started development of serial 112G electrical designs, which will be the next big step for the market. ML and AI could not grow without low–cost, high-speed networks, and 112G serial will allow switch technology to move from 12.8Tbps to 51.2Tbps or greater speeds over just a few years. To hint at things to come, events like OFC featured several cool next-generation offerings ushering in that next great thing.

Authored by: Alan Weckel, Technology Analyst at 650 Group